Judging from the datasheet, I think AD9142 can only reach a DCI as high as 250MHz in 2x interpolation mode. However, we tried a DCI of 800MHz to perform a chirp pulse from 10MHz to 400MHz(digital pattern generated from a DPG3). The screen shot is attached below with some details marked on it.
So I've got several questions:
1, What's the maximum f-interface available for users? 250MHz or 800MHz
2. What's the difference between MHz and Mbps when talking about a reference bit's frequency, especially when it's a double data rate data sampling clock? You know when referring to the "digital clock input"(DCI), the datasheet use both f-INTERFACE(page 8) with Mbps as its unit and f-DCI(page 22) with MHz as its unit and that makes me confused. I think that f-INTERFACE doesn't represent the DCI frequency but the frequency of the whole LVDS interface but it makes me further confuse because we know two words(32 bits for both I and Q data, according to Figure 33) are transmitted through the 16bit LVDS interface during one DCI time period, that's actually 2 bits at a frequency of 200MHz for each data bit of the interface, but f-INTERFACE is still said to be 200Mbps in 8x interpolation mode to achieve a sample rate of 1.6GSa/s. So would you please kindly give me a introduction of the definition of confusing parts:
a, Difference between MHz and Mbps when referring to a word clock.
b, Difference between MHz and Mbps when referring to a double data rate data sampling clock.
c, Difference between the data bit frequency unit and the reference bit frequency unit.
d, Difference between the data bit frequency unit and the reference bit frequency unit when it's a double data rate interface.
3. Can the power supply circuit on the evaluation board meet the requirement listed in the first figure's upper right corner.
4. Any updates about AD9138? Judging from the evaluating guide it's believed to have a interface frequency of 600MHz at least.