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how to implement bidirectional 32 bit standard 4 wire spi master mode

Question asked by on Aug 23, 2013
Latest reply on Sep 5, 2013 by MaheshN


Dear ADI specailist and Fans:


I want to driver adas1000 (ADI ECG front-end) with sharc 21489.


But I found it's difficult to implement bidirectional 32 bit/16bit communication through standard 4 wire spi protocol in DMA master mode.


Since reference code of adas1000 driver is written for Blackfin BF527 by using SPORT interface, I also tried to use SPORT1/2 to simulate spi bus. But in the end, I found it's crazy that the first cycle (fsync low) is something beyond my understanding - double width (64bits) of valid word length (32bits) and contains all zero values. Afterwards, the communication restored as what I expected (32 bits width and valid value as I send out).


The result is observed in logic analyzer when Sharc works in master DMA mode. Attached packae 1 is source code, please help me to find why. I have been pending on this issue 1 week.


After comparison of spi and sport inerface in sharc hardware spec, I found it seems spi interface can only support one directional dma. For example, in master mode, it can only set up the only DMA channel (attached to this spi interface) in tx or rx only mode.


In hardware spec:

DMA Master Transfers

To configure the SPI port for master mode DMA transfers:

1. Define DMA receive (or transmit) transfer parameters by writing

to the IISPIx, IMSPIx, and CSPIx registers.

2. Write to the SPIDMACx register to enable the SPI DMA engine

(SPIDEN, bit 0). And configure the following:

• A receive access (SPIRCV = 1) or

• A transmit access (SPIRCV = 0)


So I want to know if spi bus works in half duplex mode actually in DMA master mode? For example, assumed I set up receive access mde, SPI bus will activate CS signal continuously until RX DMA finished. In this procedure, MOSI signal should be totally useless (salve device don't care), and MISO signal would be captured into RX DMA FIFO register.


Oppositely, in transmit access mode, MISO signal is useless - it's ignored by sharc.

Am I right?


If my understanding is right, how can I implement full duplex mode DMA - parralel TX/RX DMA in master mode? It seems the only answer lies in sport interface.


In conclusion, I want some guy can help me to do:

1) Modify attached sharc21489 sport driver example to implement valid bidirectional dma in master mode without first cycle error.

2) Give a simple sample code to demonstrate spi dma master (32bits) mode for tx and rx only dma mode in sharc21489. Of course, if full duplex mode is avaliable, please also give me example as well.


Since there's little reference code or applciation note about sharc 21489 spi/sport interface, please ADI guys do take some time to help me to achieve this - I'm already weared out for this issue.


Thanks very much!