Hello, I am in charge of maintaining VHDL code (from a person that left) for an interface to the AD7176-2 and I have some questions in order to debug the circuit:
1- When set to Continuous Conversion Mode (default), does the conversion start from the first channel every time the CS is low? In other words, does the ADC restart the conversion cycle whenever the CS transistions from high to low?
2- When the DATA_STAT bit is set, the datasheet specifies that the Status reg is appended to the Data out. In 24-bit mode data mode, for example, is the 8-bit Status reg appended before the actual data or after the data is clocked out?