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AD9915 Multi-chip Synchronization

Question asked by hanseyo on Aug 21, 2013
Latest reply on Aug 23, 2013 by LouijieC


I have several questions for multi-chip synchronization of 9 DDSs using AD9915 as below.


1. Do I have to send the IO_UPDATE signal to each DDS separately?. Actually I configured DDS sequentially and then sent a common IO_UPDATE with sufficient pulse width. Is it wrong?


2. I configured 9 DDS for multi-chip synchronization as below

    1) DAC CAL enable: Set CFR4[24] with USR[6] = 0, CFR2[9:8] of master = 11, CFR2[9:8] of slave = 01

    2) waiting for 444us (=531,840/1.2GHz)

    3) DAC CAL clear : Clear CFR4[24]

As a result I did like above, I could confirm synchronization of SYNC_CLK for each DDS. But each DDS IF output is not synchronized.

If I say about our test environment, I use 1.2GHz as a reference clock. It is supplied externally using cable by PLO and divider. So each ref. clock is not edge aligned. But we can align the phase of PLO output by re-assembling PLO. Is it possible of multi-chip synchronization though each ref. clock is not edge aligned?

As a result of synchronization of SYNC_CLK, DAC calibration is OK but each DDS IF output is asynchronus.

I don't know the reason of this result.


Please give me your advice.


Thank you.