I'm running Sigma Studio 3.8 and using the ADAU144x part. In working with the AB in CD out Condition module, I've run into what looks like a headroom issue.
I stand/beg to be corrected here, but based on the 5/23 format of stating levels, I think that Sigma should be able to accommodate a level to about 15 with its 28-bit internal architecture. I'm using the ABCD module in the 'greater than' mode to compare A and B levels in the 0.1 to 1 level range, and attempting to switch a DC level of 10. (This is to "hurry along" an integrator during a specific event.)
I have a DC Input Entry source set to 10 going into the C input of the block, and am looking at D with both the Real Time Display and a Readback module. When A goes greater than B, I don't see a 10 coming out. If I scale down the DC to a 1, then everything seems to work. Am I violating something here? This reminds me of smacking against the substrate in a 4066 CMOS switch.