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ADV7604 CSC/Clamping for DVI RGB pass thru mode

Question asked by ppg on Aug 13, 2013
Latest reply on Aug 23, 2013 by joe.triggs

Hello,

I am using ADV7604 for DVI/Analog receiver application.

The input in DVI mode is 24 bit RGB and I am expecting the chip to give 24 bit RGB on output lines.

I am having trouble finding settings to enable data pass thru (with no CSC/clamping) similar to discussion @

http://ez.analog.com/message/68505#68505

I am sending solid color screens using a pattern generator, and I have verified with ADV7612, and the pattern on DVI lines is indeed what I am sending. But on ADV7604, the data is changing and it appears like some scaling/clamping is happening.

I have tried with various INP_COLOR_SPACE settings, but I am not able to get the exact data that I am sending.

Can someone advise on what I am missing and how the chip can be put into a mode where it can "simply" pass input video in received format to output lines.

Thanks

 

I use following settings:

 

    /* based on the ":DVI script:" section in ADV7604IO_ADV7604CP_

     * ADV7604AFE_ADV7604HDMI_ADV7341B-VER.1.4c_RevA.txt and

     * "ADV7604 Register Settings Recommendations(rev.2.5,June 2010)" */

    io_write(sd, 0x00, 0x02);   /*VID_STD = 0x2, */

    io_write(sd, 0x01, 0x86);   /* Prim_Mode = 110b HDMI-GR */

    io_write(sd, 0x02, 0x12);   /* RGB 0-255 in, RGB out */

    io_write(sd, 0x03, 0x40);   /* 24 bit SDR 444 mode 0 */

    io_write(sd, 0x04, 0x62);   /* op_ch_sel = 0x03 */

    io_write(sd, 0x05, 0x28);   /* AV codes off */

    io_write(sd, 0x06, 0xa6);   /* VS and HS inverted */

    io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */

    io_write(sd, 0x14, 0x7f);   /* Drive strength adjustment */

    io_write(sd, 0x15, 0xa0);   /* Disable tristate of pins */

    io_write(sd, 0x33, 0x60);   /* LLC DLL Mux Enable */

 

    /* component processor */

    cp_write(sd, 0x69, 0x30);   /* enable CP CSC for pass thru mode HW Manual RevF Page 216*/

    cp_write_and_or(sd, 0xc9, 0xfe, 0x00); /*DIS_AUTO_PARAM_BUFF = 0 */

    cp_write(sd, 0xcf, 0x01);   /* Power off macrovision */

    cp_write_and_or(sd, 0xbd, 0xff, 0x10); /*bypass DPP EN*/

    cp_write(sd, 0x3e, 0x00);  /* CP core pre-gain control */

 

     /* analog front end */

    afe_write(sd, 0x00, 0xff);   /* Power down ADCs & their assoc. clocks */

    afe_write(sd, 0x01, 0xfe);   /* Power down ref buffer/bandgap/clamps/sync */

    afe_write(sd, 0x13, 0x93);   /* Set LLC DLL phase */

    afe_write(sd, 0xb5, 0x01);   /* Set MCLK to 256Fs */

    afe_write(sd, 0xc8, 0x40);   /* ADI recommended setting */

 

    /* HDMI */

    hdmi_write(sd, 0x01, 0x00);  /* Enable clock terminators */

    hdmi_write(sd, 0x0d, 0x84);  /* ADI recommended write */

    hdmi_write(sd, 0x15, 0x03);  /* Set audio FIFO mute masks */

    hdmi_write(sd, 0x1a, 0x0a);  /* Set mute delay to 1_5sec */

    hdmi_write(sd, 0x3d, 0x10);  /* ADI recommended setting */

    hdmi_write(sd, 0x3e, 0x39);  /* ADI recommended setting */

    hdmi_write(sd, 0x48, 0x06);  /* Set audio FIFO reset */

    hdmi_write(sd, 0x57, 0xb6);  /* Enable dynamic PLL control */

    hdmi_write(sd, 0x58, 0x03);  /* Recommended PLL setting */

    hdmi_write(sd, 0x59, 0xa3);  /* ADI recommended setting */

    hdmi_write(sd, 0x8d, 0x18);  /* ADI recommended equalizer setting */

    hdmi_write(sd, 0x8e, 0x34);  /* ADI recommended equalizer setting */

    hdmi_write(sd, 0x93, 0x8b);  /* Equalizer ADI recommended setting */

    hdmi_write(sd, 0x94, 0x2d);  /* Equalizer ADI recommended setting */

    hdmi_write(sd, 0x96, 0x01);  /* Enable automatic EQ changing */

    hdmi_write(sd, 0x1a, 0x0a);  /* Unmute audio */

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