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Why FMCOMMs1 output does not match input?

Question asked by mmauri on Aug 12, 2013
Latest reply on Sep 12, 2013 by charlyelkhoury

I am using the FMCOMMs1 with a ML605. I got the reference design to work fine. I decided to switch a complex signal instead of the Sine-Cosine function from DDS. I've been able to get the outpu to match the input sometimes but it is not consistent. Some times I have to run the intialization software multiple times to get it to work.


Currently  the data path is setup to bypass every stage: F/2 Premod, NCO, HB1, HB2, HB are all bypassed..


What do I have to do on ensure that the data always match? I've been struggling with this for a while and I think I am close but ran out of ideas.


The only change I made to the DAC core waw to add a multiplexer to allow switching between DDS and external signal. The external data is clocked with the DAC_Div3_clk.


Here is the mod I made to the DAC core module cs_ddsx.v:


// mod by manuel to add Input from the transmitter

// dds_data_00 <= {(dds_format_n ^ dds_data_out_00[15]), dds_data_out_00[14:0]};

// dds_data_01 <= {(dds_format_n ^ dds_data_out_01[15]), dds_data_out_01[14:0]};

// dds_data_02 <= {(dds_format_n ^ dds_data_out_02[15]), dds_data_out_02[14:0]};

// dds_data_10 <= {(dds_format_n ^ dds_data_out_10[15]), dds_data_out_10[14:0]};

// dds_data_11 <= {(dds_format_n ^ dds_data_out_11[15]), dds_data_out_11[14:0]};

// dds_data_12 <= {(dds_format_n ^ dds_data_out_12[15]), dds_data_out_12[14:0]};


dds_data_00_i <= {(dds_format_n ^ dds_data_out_00[15]), dds_data_out_00[14:0]};

dds_data_01_i <= {(dds_format_n ^ dds_data_out_01[15]), dds_data_out_01[14:0]};

dds_data_02_i <= {(dds_format_n ^ dds_data_out_02[15]), dds_data_out_02[14:0]};

dds_data_10_i <= {(dds_format_n ^ dds_data_out_10[15]), dds_data_out_10[14:0]};

dds_data_11_i <= {(dds_format_n ^ dds_data_out_11[15]), dds_data_out_11[14:0]};

dds_data_12_i <= {(dds_format_n ^ dds_data_out_12[15]), dds_data_out_12[14:0]};


dds_data_00 <= (sel_inp == 1'b1) ? xmit_re : dds_data_00_i ;

dds_data_01 <= (sel_inp == 1'b1) ? xmit_re : dds_data_01_i;

dds_data_02 <= (sel_inp == 1'b1) ? xmit_re : dds_data_02_i;

dds_data_10 <= (sel_inp == 1'b1) ? xmit_im : dds_data_10_i;

dds_data_11 <= (sel_inp == 1'b1) ? xmit_im : dds_data_11_i;

dds_data_12 <= (sel_inp == 1'b1) ? xmit_im : dds_data_12_i;

// End of Input from the transmitter




Here a ChipScope display of the input to the DAC(top)  and the Output from the ADC (bottom). This is one of the time when the output did not match. If I rerun the software multiple times there times when the output matchs the input, and even then one of the channels is inverted.




Message was edited by: manuel mauricio  Added Chipscope display.