I have a custom made board based on the BF548 processor and have a question regarding the SPORT interface.
I have the following situation :
I am using SPORT1 as RX with external clock and also external RFS. The clock and the RFS are generated by GP Timers from the same BF548 processor. These GP Timer generated clock and frame are also applied to a external chip for clocking in serial data into the BF548 through SPORT1. This external chip expects a Chip Select and a clock as input.
I have troubles with the DMA unframed mode , because the number of DMA interrupts in a given period is not equal to number of times I triggered the clock and the frame . So I have a sync problem here I believe.
When using the DMA framed mode I don't have the above mentioned problem , but still I received junk data. In the framed mode , a frame sync is required for each word transfer, but actually I am using only one frame sync (late frame) for 64 clocks period. I am not using 4 frame syncs for each 16 bit word. Maybe it is worth mentioning that I am using the Primary and Secondary for receiving data. So I am receiving in total 8 x 16 words in the FIFO . This data is supposed to be DMA'ed to my memory location.
I think it is strange that the DMA is working properly but the data is junk. The reason why I am not using 4 frame syncs is because the external chip expect one frame sync of 64 clocks. I think that I can bypass this by using an additional timer to emulate the required signals but still , I am wondering why the one frame sync is not working .
Is the reason for receiving junk data is because I am not using a frame sync for each word ??
Why then is the DMA gives an interrupt after the 8x 16 words properly ?? I assume because there is no 4 frame syncs , it should not fire an interrupt.
Looking forward for a reaction ..