I'm designing circuit with AD9626 as 16Mhz sampling clock.
And I have questions following.
1. From data sheet, on figure2 Data output is using interleaving.
Odd 8 bits on falling edge of DCO, Even 8bits on rising edge of DCO.
Is it correct? But in page 23, there is represented "the CMOS data outputs are
valid on the rising edge of DCO."
What is correct sentence?
2. In "Clock input considerations", there are describing ac coupled clock input.
But I will supply LVCMOS single-ended clock from CPLD.
I think 16Mhz low speed clock doesn't need consideration of jitter.
Thus I can supply normal 1.8V CMOS single-ended dc-coupled clock to ADC.
Is it correct?
Really, I can't understand figure 45 clock input circuit.