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AD7762 MCLK buffering requirements

Question asked by on Aug 7, 2013
Latest reply on Aug 22, 2013 by MClifford

. what is the minimum voltage required for the clock input (MCLK). I'm using a Crystal and gate buffer as per ad7760 evaluation board design, frequency is accurate but the max voltage of the clock source is 2v.

data sheets show MCLK voltage to be 5V.


This is my first time with high speed AD's. Please let me know if the MCLK has to be strictly 5V at 40Mhz. Also suggest if there any other oscillator configuration I should try.