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data transfer through DMA's  external port

Question asked by gunnros on May 11, 2010
Latest reply on May 12, 2010 by jeyanthi.jegadeesan

Hi,

 

I 'm working on Adsp - 21065L platform and  VisualDSP release 4.5.

 

My task is to interface an external device (MCU) through DMA's external port channel 8 , e.g. using EPB1 buffer, configured in handshake, for transfering a single 16 bit word every ms. The parameter registers are set as follows:

 

IEP1 = oxoooodooo

IMEP1 = 1;

CEP1 = 1;

 

Data transfers are completed succesfully, but...

 

Fistly, when configuring DMAC1 register in my code i observe that some instructions do not actually affect some bits. Particularly, this happens when i disable chaining by setting chen - 0 and CPEP1 - 0x0000 but DMAC1 register window shows it active (it was initially).

 

The thing is that i want the proccesor to "knows" when a single word tranfer is done so as to start proccesing....but,  DMASTAT steadilly shows this value:

which comes with disagreement with what DMAC1 shows (channel's active) and so polling does not work for determining the end of a transfer.

 

When i unmask DMA interrupts, no interrupt is generated when counter register decreaments to zero although i set PCI bit at CPEP1 register ( i do that to enable interrupts cause as i said chaining seems unaffected and active). So, i ask: am i missing something or shall i talk to the support?

 

Thanks,

 

Michael

 

_____________________________________________________________________________________________________________________________

Here's my code

 

                                                       // note: DMA_ISR is mapped at "isr_tbl.asm" interrupt vector table file

#include <def21065L.h>

#include <signal.h>

//#include "new65Ldefs.h"

 

#define SAMPLING_PERIOD 0x11E0B8AB     //0x0000EA54: 1ms

#define JUMP_INSTR_OPCODE 0x063E0000

#define RTI_INSTR_OPCODE 0x0B3E0000

#define TMZLI_VEC 0x0000805C

#define FLAG10O 6

#define FLAG10 6

 

.GLOBAL main_routine;

.GLOBAL TMZLI_isr;

.GLOBAL DMA_ISR;

 

.segment /dm dm_data;

 

.VAR index = 0;

 

.endseg;

 

 

.segment /pm pm_code;

 

main_routine:

 

    call place_timerISR;

    call set_timer;

 

    R0 = dm(IOCTL);

    R1 = 0x4B;

    R0 = R0 OR R1;;

    dm(IOCTL) = R0;

 

    R2 = dm(IOSTAT);

    R2 = bset R2 by 1;

    R3 = 0xBD;

    R2 = R2 AND R3;

    dm(IOSTAT) = R2;

 

    call set_DMA;

 

    NOP;

 

/*wait_trf_comlp:

 

   R14 = dm(DMASTAT);

   btst R14 by 7;

   if NOT SZ jump wait_trf_comlp;

   bit clr mode2 TIMEN0;

   R2 = dm(IOSTAT);

   R2 = bclr R2 by 3;

   dm(IOSTAT)= R2;*/

 

 

_sit:

    NOP;

    idle;

    jump _sit;

 

 

main_routine.end:

 

 

place_timerISR:

 

    PX2 = JUMP_INSTR_OPCODE;

    PX1 = TMZLI_isr;

    pm(TMZLI_VEC) = PX;

    PX2 = RTI_INSTR_OPCODE;

    PX1 = 0;

    pm(TMZLI_VEC + 1) = PX;

    pm(TMZLI_VEC + 2) = PX;

    pm(TMZLI_VEC + 3) = PX;

    //FLUSH CACHE;

            RTS;  

 

 

set_timer:

 

 

   bit clr mode2 TIMEN0;

   bit clr mode2 INT_HI0;

   bit set mode2 PWMOUT0 | INT_HI1;

   bit set mode1 IRPTEN;

   bit clr mode1 NESTM;

   bit set IMASK TMZLI;

   R1 = SAMPLING_PERIOD;

   dm(TPERIOD0) = R1;

   R2 = 1;

   dm(TPWIDTH0) = R2;

   bit set mode2 TIMEN0;

   RTS;

 

TMZLI_isr:

 

   R8 = dm(IOSTAT);

   //R7 = FLAG10;

   R8 = bset R8 by FLAG10;

   dm(IOSTAT) = R8;

   R3 = dm(index);

   R3 = R3 + 1;

   dm(index) = R3;

   R7 = 0x01;

   R4 = R3 AND R7;

   if EQ jump even;

 

 

odd:

 

   R6 = dm(IOSTAT);

   R6 = bset R6 by 0;

   dm(IOSTAT) = R6;

   jump intr_end;

 

even:

 

   R6 = dm(IOSTAT);

   R6 = bclr R6 by 0;

   dm(IOSTAT) = R6;

 

intr_end:

 

 

   R8 = dm(IOSTAT);

   R8 = bclr R8 by FLAG10;

   dm(IOSTAT) = R8;

 

   RTI;

 

TMZLI_isr.end:

 

set_DMA:

 

   R12 = dm(DMAC1);

   R12 = bclr R12 by 0;

   dm(DMAC1) = R12;

 

   R5 = dm(DMAC1);

   R7 = 0x0440;

   R5 = R5 OR R7;

   dm(DMAC1) = R5;

 

   R5 = dm(DMAC1);

   R7 = 0xC459;

   R5 = R5 AND R7;

   dm(DMAC1) = R5;

 

   R10 = 0x0000d000;

   dm(IIEP1) = R10;

   R5 = 1;

   dm(IMEP1) = R5;

   R6 = 1;//20;

   dm(CEP1) = R6;

   R0 = 0x00000;

   dm(GPEP1) = R0;

   R14 = dm(CPEP1);

   R13 = 0x0000;

   R14 = R14 AND R13;

   //R14 = bset R14 by 17;

   dm(CPEP1) = R14;

   R4 = 0x00080000;

   dm(EIEP1) = R4;

   dm(EMEP1) = R6;

   bit set IMASK EP1I;

   R4 = dm(DMAC1);

   R4 = bset R4 by 0;

   dm(DMAC1) = R4;

 

   RTS;

 

 

DMA_ISR:

 

   bit clr IMASK TMZLI;

   R12 = dm(DMAC1);

   R12 = bclr R12 by 0;

   dm(DMAC1) = R12;

   R2 = dm(IOSTAT);

   R2 = bclr R2 by 3;

   dm(IOSTAT)= R2;

   RTI;

 

DMA_ISR.end:  

 

.endseg;

 

 

 

DMASTAT = 21AD6B5A

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