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ADCLK948 output clock issue

Question asked by krishh414 on Aug 2, 2013
Latest reply on Aug 5, 2013 by Kyle.Slightom

Hi,

      we are using ADCLK948 to distribute 50/60 Mhz clock to three AD9650 ADC's synchronously.When checked Signal Integrity using IBIS models, the output swing of ADCLK948 is nearly 1Volt, where 0.8V is the permissible value.I am attaching the files required please hellp me on this issue, Thanks in advance.

Regards,

Krishna Chaitanya.

 

differential Signal.bmpdifference Signal.bmp

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