I am trying to get this reference design for the AD9467 http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467 to work on the Zedboard part#:xc7z020clg484-1. I attempted to run the batch file but I assume it is a configuration issue with the MHS file?? Here's the terminal output
After that I opened xps file and attempted to replace the two IPs that were out of date axi_dma and the processing system... I was able to connect most of the components back but I am not sure why I can't connect the delay_clk of the user axi_adc_1c to the FCLK1 or any of the PS clocks for that matter
Am I going down the right path with this???