I have the AD9467 FMC dev board connected to a Kintex-7 KC705 eval board. I'm failing to get timing closure for the adc data input pads to the DDR registers. The problem is the PVT differences for fast and slow corner process timing analysis between setup and hold is such that shifting the clk phase will never satisfy the worst case for both.
Part of this might be my interpretation of the data valid window from the AD9467 datasheet. I've looked at the verilog HDL files for the reference design provided for the KC705 but see no reference to proper input OFFSET DELAY UCF constraints. Can someone confirm or even provide timing (TRCE or post synthesis analysis) results for the reference design?
My best attempt has 1 path fail by 70ps with the following HDL:
adc_clk_pad > MMCM (for phase control) > BUFG > BUFIO > IDDR2 registers
adc_data_pad (p/n) > IBUFDS > IDELAYE2 > IDDR2 registers
My interpretation of timing constraints: Datasheet (Rev C) specifies (page 7) tskew (DC0 to data delay) as +/-200ps and a rise/ fall time of 200ps. For me the diagram shows tskew from the mid point of a clk transition to the mid point of a data transition. So for a 2ns data period the first and last 300ps are uncertain leaving a valid data period of 1.4ns. My DDR constraints are pretty much:
TIMEGRP <adc_data_nets> OFFSET = IN 3.7 ns VALID 1.4 ns BEFORE "adcClk" RISING
TIMEGRP <adc_data_nets> OFFSET = IN 3.7 ns VALID 1.4 ns BEFORE "adcClk" FALLING
I could change the Offset to -300 ps (data stable 300ps after clk) but it makes no real difference and is easier to analyse looking at the next edge. Below is an example of my timing (before using the IDELAY and BUFIO) where the slack differences were about 400ps too big: