Hi, there

I'm trying to implement a CIC decimation filter and it doesn't work, I think due to problems with integrators overflow. The CIC is 4 stages, decimation ratio = 8 and differential delay = 1. I'm working with fp 1.15 and I'm using the normal sum (allows overflow) instead add_fr1x16 to avoid saturation. Furthermore, to compensate the gain of integrator, the feedback is divided by 8. The simulation in Matlab (floating point) works well until the integrators saturate.

The data to process is 12 bit-width, so I think that with 14 bits for intermediate processes should be enough (12 + log2 (4)) (*), but I'm not sure.

In the other hand, is it necessary that the width of data in the integrators and differenciators is the exact number of bits of (*) or can it be greater ? Is the overflow affected by this?

Any help will be appreciated, thanks in advance

Hi,

Welcome to the EngineerZone. I have moved this question from the Processors and DSP community to the Blackfin Processors community. Please continue the discussion here.

Regards,

Craig.