I'm having some problems with a spur on the AD9958.
I use a 25MHz XTAL and multiplies it with the PLL to 500 MHz. Actually there are spurs around my 100MHz output frequency spaced at 25MHz from the carrier. First I thought it was the reference spur from the PLL that mixes with my output (because of the 25MHz reference clock). But when using an external 500MHz clock it has the same spectrum.
So I think the spurs are comming from the Fsys/4 (500/4 => 125MHz) that create more IM products with my carrier. Can this be correct?
If so, can these spurs be reduced by disabling the SYS_CLK pin in the registers or would that have no effect? the SYS_CLK on my board is not terminated with any resistor witch I should have done I think, or not?
Below the spectrum is included. The 125MHz is like 40dB below carrier. The problem is that it creates 10 ps jitter of the total 14 ps. If this can be disabled or reduced, the clock will be much better.
Thank you in advance for help.