I am trying to effort to configure the AD9915 using parallel mode. I done configuration logic xilinx FPGA and use a 25MHz as configuration clock.
But I couldn't see the SYNC_CLK from pin-82 of AD9915 and couldn't read back register also.
I did as below.
1. power-up the board
2. confirmed the reference DDS input clock of 2.5GHz
3. send the master reset
4. confirmed the DDS external power down pin
5. confirmed if the SYNC_CLK appeared at pin-82 or not but I couldn't see the SYNC_CLK
Parameter setting is same as below.
Address Name Value
0x00 CFR1:LSB 0x0308
0x02 CFR1:MSB 0x0001
0x04 CFR2:LSB 0x0A00
0x06 CFR2:MSB 0x0040
0x08 CFR3:LSB 0x191C
0x0A CFR3:MSB 0x0000
0x0C CFR4:LSB 0x3120
0x0E CFR4:MSB 0x0005
0x2C Profile0FTW 0xB852
0x2E Profile0FTW 0x051E
0x30 Profile0POW 0x0000
0x32 Profile0ASF 0x07FF
0x6C USR0:LSB 0x0800
0x6E USR0:MSB 0x0000
I attached the capture file of xilinx chipscope.
where, LSB of address bit is truncated.
Please let me know read-back and SYNC_CLK confirmation method.