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AD9910 , strange registers behavior

Question asked by hiro.sp on Jul 25, 2013
Latest reply on Aug 7, 2013 by sitti

Hello, forks

 

I designed my AD9910 board and programming it but I met some strange behavior of AD9910 registers.

 

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(1) CFR1  RAM enable and RAM destination cleared automatically when profile change

debug log:

000 : %%%  debug start disp ad9910 %%%

001 : READ: CFR1 = 00:C0:00:00:02

002 : prof = 0    IO OUT

003 : CFR1 read    = 00:C0:00:00:02

004 : RAM read= 16:3F:F0:00:00

005 : prof = 1    IO OUT

006 : CFR1 read    = 00:00:00:00:02     <=== !!!!! unexpected change

007 : RAM read= 16:1F:F0:00:01

......

RAM en, and RAM dest. is cleared at line#006 after  profile port  change.

I can't image the reason of it.  it just port profile [2:0] changed. but why ?

this phenomena occurs in first time after initialize reg.

[ SOLVED, descl below  ]

 

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(2) cant change  CFR1 External power-down control, Is it reflects hardware port condition ?

000:  ad9910 verify 

001:  CFR1 wrote= 00:c0:00:00:02

002:  CFR1 read=  00:c0:00:00:0a  <===== !!!!! not same value but EXT_PWR_DWN is active==1 at this line

The register value is mismatch  read/write

and it seems bit3 indicates hardware condition (18 pin EXT_PWR_DWN )

when ext hw pin is zero, value is meet 0x02

but, I can't find description about it in the data sheet.

 

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(3) External power-down control bit  means 0:full  1:FAST  is inverted ???

I measured consumption current each FULL-PD and FAST-PD active,

but FAST-PD 's current is less than FULL-PD's.

That is reverse status that I expected.(I think that FULL-PD has slow recov.time but more less current)

 

Please advice for me.

Thanks.

 

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I solved "(1) CFR1 unexpected change" . the reason is register POW displayed before the sequence, The POW register has just size 2 byte while other register is 4. so, displaying POW executed cmd 0x00, 0x00 as side effect. it writes CFR1 but not updated register content. after it, the port PROFILE changing makes CFR1 update . It's  just my own software bug.

 

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It's my hypothesis, External power down control Bit(CFR1-BIT3) is   0:FAST,  1:FULL . (it's reverse from data sheet)

and while FULL power down state, register change is not allowed.

so, issue(2)  phenomena  means  register wouldn't change while FULL-PD activated.

and issue(3) also explained by  phenomena of issue(2)

I think it's a errata of datasheet.

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