I have been working with the ADV7403 chipset for a few weeks now. I started another thread asking about a test script. I will post more there.
However, I have started this thread because the end top resolution for our system requirements is 1280x800 @60Hz. The specific VESA version is the reduced 1280x800. This means that the pixel clock is 71MHz. The specific panel to be used (for now until I have time to get back to the graphics processing side) is configured to have a 71MHz pixel clock, 1440 samples in each line and 823 total samples in the entire frame (then repeat at the refresh rate).
I have followed the Application note for starting with a standard setting and then adjusting parameters. The only requirement on the system is to facilitate a VGA input of 1280x800 to a graphics processor and then overlays and other items are digitally inserted. On the custom test board which is a relative copy of the evaluation design, I have a path to connect through buffers the ADV7403 to the screen. I have configured it using the VID_STD and PRIM_MODES to show 1024x768 and with a 1024x768 image I can view it on the final panel as well as a smaller panel which is native 1024x768.
I am attaching the script to configure to the 1280x1024 standard and then attempt to adjust the sampling time, length, and FR_LL registers to adjust the timing parameters to reduce the number of VSYNC clocks from 1024 to just 800.
0x42 0x03 0x10 // Sends the OF_SEL for 30bit output mode
0x42 0x05 0x02 // Set for Graphics Mode
0x42 0x06 0x05 // Set for the 1280x1024 @60Hz mode
0x42 0x1D 0x47 // Set to the 28.63636MHz oscillator
0x42 0x3A 0x20 // Sets LLC clock for 55MHz-111Mhz with no ADC power down
0x42 0x3B 0x80 // BIAS Control external as well as 600uA iBIAS setting
0x42 0x3C 0x5D // Default SOG and 101 PLL_QPUMP setting
0x42 0x6A 0x1F // DLL in use and DLL_PH adjust is full *May not be necessary*
0x42 0x6B 0x80 // HSYNC out and DE out instead of field. CPOP_SEL for 30 bit
0x42 0x7C 0x90 // Negative Pol HS, Pos Pol VS and DE, START_HS=00xxxxxxx END_HS = 00xxxxxxx
0x42 0x7D 0x00
0x42 0x7E 0x00
0x42 0x7F 0x00
0x42 0x87 0xE5 // Settings for PLL MANual settings PLL_DIV_RATIO[11:0] = 0x5A0 or dec 1440
0x42 0x88 0xA0
0x42 0x8A 0xD0 // Sets VCO Range
0x42 0x8F 0x02 // Sets FR_LL = 0x244 which is the calculated based on 1440 Luma Samples
0x42 0x90 0x44 // and Frequency of 71MHz. (1440/71MHz)/(1/28.63636MHz) = 244h
0x42 0x77 0xFF // Sets up the CP_OFFSET1
0x42 0xB3 0x54 // Sets the DPP_CP_98 register
0x42 0xBF 0x06 // Next settings are for strength and blue mode
0x42 0xC0 0x00 // Next settings are for strength and blue mode
0x42 0xC1 0x87 // Next settings are for strength and blue mode
0x42 0xC2 0x00 // Next settings are for strength and blue mode
0x42 0xF4 0x2A // Medium drive strength
The problem I am having is that when I have a correct 1280x800 @60Hz and 71MHz pixel clock, I have synchronization (i.e.: the blue screen goes away) but a valid image is not really showing on the screen. I am having a hard time determining if there is any way to adjust the vertical resolution down from 1024 to 800 or in another manner would be to stretch at 1024x768 image up to 1280x800? What would be the preferred method? I have been scouring the EngineerZone site and have not found this specific issue on the 7403 (or family of I2C chips) and am wondering if someone could provide insight.
I have downloaded all support files and manuals from the engineer zone on the 7403 and the "ADV7403_Manual_RevB" has been my best guide so far.