We have a AD9779 in our design and we are supplying it data from an FPGA. The data sent from the FPGA is either a CW (0, 0x7FFF, 0, 0x8001...) or broad band noise. In the FPGA, we then "right" bit shift the data (maintaining the sign bit) in order to digitally attenuate the power by -6db per shift. In both cases (noise and CW) we see expected results up to about 5 shifts. I.e. 1 shift = 6db drop. After 5 shifts the DAC output does not behave as expected. From shifts 5-7 tt drops by successively less amounts (less than 6db). After 8 shifts the output actually starts increasing. We have tried many different register settings. The latest are attached. Do you have any insight into this behaivor? We expect to be able to control the DAC output all the way to the last couple of bits.
2 Real independent signals on I and Q channels
Fdac = 250 MHz
Fdac/2 Modulation = 125MHz
FPGA-DAC Data Rate = 125MHz
The current design uses the AD9779 part but we want to switch over to the AD9779A part. Are there any differences between the parts with respect to this issue?
Thanks in advance.