Can I set AD9837 to output the DAC msb and have the ability to set freq in 10-15hz increments from 800khz to 2.5Mhz (MCLK=16mhz)?
Will the amplitude of Vout be the digital 2.5v or something else, VDD=3.3V?
If you want to output the MSB, the output voltage is Vdd.
With a 16MHz clock, you have a resolution of 16MHz/2^28=0.06Hz
I am afraid I don't see how that resolution is possible.
If I have a 16Mhz clock feeding the chip, then the internal logic is running on a 62.5ns period clk, and if I have have it programmed for a 1Mhz output clk via the MSB bit, the best I can do is change the period of of the output from
1000ns to 1062.5ns, the freq just changed from 1Mhz to 941.176khz. No where near the resolution you spoke of.
Please help me to understand where my thinking is wrong.
Im afraid but I cannot understand your reasoning...
The MCLK period is internally divided (phase accumulator) so, your minimum increment is 0.06Hz.
let me try it this way, I am using the DAC MSB bit output as a clock, do you think if I change the freq register from 1Mhz to 1.01Mhz ( a 10000 hz change) , and I have an oscilliscope on the signal, do you think I will see the period of the signal change from 1000ns to 990.09 ns? I don't think so. I think there is a reason the data sheet calls this signal a "coarse clock".
I am guessing this, if you looked at the signal over hundreds of cycles, drove a freq counter with it, it might in fact read 1.01Mhz, but that would be due many clocks at a 1000ns period, and a few at 937.5ns period.That the only 2 availabe periods available given a signal coming from logic clocked at 16Mhz
f = 1/t
for an increment of 10kHz => 100us
16MHz => 62.5ns
100us / 62.5ns = 1600 clocks
answering your question, yes, you will see a change in your output signal period.
The MSB is connected to the phase accumulator, not to the Mclk.
You can find more info here,
Thank you so much taking the time to reply, I am really trying to understand, I think I will ultimately have to get an eval board for and play with that.
I followed your link to the document, and it seems to me it supports my concern, from page 49, it says the MSB bit of the DAC will have 1 clock cycle of jitter, thats 63.5ns for AD9837 with 16mhz ref clk, see below.
I am thinking I should be looking at the 9838 since it has ability to convert the DAC sine wave into square wave. And via the text of the document you refered me to, the jitter should be much less that that of the DAC MSB.
Page49: The DDS Clock GeneratorThe DDS output is a sampled sine wave containing many extraneous frequency components that
The DDS Clock Generator
The DDS output is a sampled sine wave containing many extraneous frequency components that
will create jitter if used “as is”. The amount of jitter resulting from an unfiltered sampled sine
wave is equal to 1 input clock cycle. If a clock cycle is 5.7ns (175 MHz) then that much jitter
will be observed from an accumulation of adjacent cycles of the DDS output signal. Figure 1
shows an unfiltered sampled sine wave from a DDS being clocked at 175 MHz. Only about 3
samples per cycle are being synthesized; however, the cycle-to-cycle samples are different as is
evident by the change in voltage levels of the samples as they progress from left to right. This
waveform represents about 56 MHz. When this signal is routed to a comparator with a fixed
zero-crossing threshold, the 1 clock period jitter becomes visible with the scope in the infinite
persistence mode. Incidentally, the jitter magnitude is the same if only the MSB of the 10-bit
input code to the DAC were to be examined.
Unless your clock output is multiple of 2^n, you will measure jitter.
To avoid this, the recommendation is to filter the sine-wave with a LPF and use a comparator, as you pointed, the AD9838 includes this component.
I know this topic is a bit old, however I have got a question about the AD9838.
In fact I got the same problem stated here with the AD9837 that's why I'm planning to update my design using the AD9837 in order to get a better square wave that I'm planning to use as a variable clock signal. However, it is stated in the datasheet that the comparator has a high pass filter with a cutoff frequency at 3MHz, and that this frequency is needed in order to operate correctly as a zero-crossing detector. But in my case I'm using frequencies varying from 0.5 to 2MHz.
My question is would that have any impact on the square wave I will get?
If yes, is there any other devices that may accept the frequency range I'm working in?
You will need to use an external LPF + external comparator.
No other workaround, sorry
Thank you for your quick reply, however I still have a tiny hope this will work since Ifnickel seams to have good results in this post using frequencies varying from 40k up to 1Mhz.
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