I have an AD9783-DPG2-EBZ which is connected to an FPGA board. Right now I am proving out the interfaces / clocking.
When observing IOUT1P and IOUT2P on an o-scope, the traces are identical. However, I am interleaving I/Q samples, per the data sheet, to the LVDS inputs. My I/Q samples are not identical, they should appear as slightly phase shifted sine waves with the same frequency & amplitude. I have confirmed that the interleaved I/Q samples are leaving the FPGA. The edges of the DCI signal are coincident with change in the data from I to Q and Q to I (i.e. DCI is high for I and low for Q). It seems as if either the I or Q samples are being ignored, and one of them is being used for both DAC outputs. As a note, I have set Q outputs to 0, and I outputs to a sine wave, and the output of IOUT1P and IOUT2P are unchanged. This seems to point to the Q value being ignored.
I am wondering if a setup issue is causing my problem. Here are some key points:
- Output sample rate is I/Q pairs @ 10MHz (20MHz data rate)
- CLK (10MHz) is output from FPGA pin (lvcmos to sma connector to j1 on eval card)
- DCI (10MHz) is also output from FPGA pin
- All data/clocks are synchronous to an FPGA clock, which comes from OSC on FPGA board.
- DCO is not used
- SEEK bit is constant low. Adjusting SET, HOLD, SMP do not significantly impact the waveform. (I am assuming this is because the sample rate is so low that adjusting where the sample occurs does not push the sample time into a different region of the input data).