AD936n Power Supply and Layout Guidelines¶
- AD936n Power Supply and Layout Guidelines
- How many power domains is required by AD936n?
- Power Supply Sequencing requirements
- How high can AD9361 power dissipation be? What is it a function of?
- What is the 1.3V power supply tolerance?
- I'm using a switch mode power supply (SMPS) but the SMPS max output capacitance is small. Should I use LDOs or can I use less capacitance?
- How can I reduce the spurs generated by my DC/DC converter? They seem to be getting into the RF portion of the system.
- Which ball supplies current to the reference oscillator input circuitry?
- Example question
How many power domains is required by AD936n?¶
The AD9361 utilize three different power supply domains:
- Main supply voltage – 1.3V (may vary from 1.267V to 1.33V),
- VDD_GPO – 3.3V (may vary from 1.3V to 3.3V),
- VDD_INTERFACE (changes depends which type of interface is in use):
- with CMOS may vary from 1.2V to 2.5V,
- with LVDS may vary from 1.8V to 2.5V,
Evaluation software outlines power domains used by each part pins as below:
Power Supply Sequencing requirements¶
The following information should eventually be put into data sheets and user guides (if not already).
All 1.3V supply balls must be connected to a supply that varies within data sheet limits. No ball can be left unconnected, even if the desire is to reduce power consumption in some sort of "super" sleep mode. Unconnected balls will result in higher current draw through protection diodes. All 1.3V supplies must come up at the same time, even if using different LDOs or DC/DC converters for different balls.
If the AuxDAC and/or the GPOs are used, VDD_GPO should be supplied with 3.3V. It is possible to use a lower voltage but the AuxDAC equations in the register map will no longer be valid. Regardless if the AuxDAC or GPOs are used or not, VDD_GPO must always be as high or higher than the 1.3V supply. This is true of a system power up event as well which implies sequencing (VDD_GPO must rise as fast or faster than 1.3V). It also places a lower limit on VDD_GPO of 1.3V. If the AuxDAC and GPOs will not be used, it is best to connect VDD_GPO to the 1.3V supply.
How high can AD9361 power dissipation be? What is it a function of?¶
Power dissipation is a function of the junction to ambient thermal resistance parameter, θJA. It is defined as the ratio of the difference in temperature from the die junction to the ambient air and the power dissipated by the die.
The maximum allowable power dissipation at any allowable ambient temperature is determined by the equation:
PD = (TJ (max) − TA)/θJA.
- TA = 85degC – Ambient Temperature (Maximum Operating Temperature in our case),
- TJ (max) = 110degC – Maximum Junction Temperature (in our case),
- θJA - Junction to Air Temperature (changes with Airflow Velocity)
- For Airflow Velocity (m/sec) = 0 -> θJA = 32.3 degC/W,
- For Airflow Velocity (m/sec) = 1 -> θJA = 29.6 degC/W
- For Airflow Velocity (m/sec) = 2.5 -> θJA = 27.8 degC/W
Calculating AD9361 Maximum Package Power dissipation at given airflow conditions:
- PD = 0.77W =(110 – 85)/32.3 for θJA = 32.3 degC/W,
- PD = 0.84W =(110 – 85)/29.6 for θJA = 29.6 degC/W,
- PD = 0.90W =(110 – 85)/27.8 for θJA = 27.8 degC/W,
What is the 1.3V power supply tolerance?¶
Base on datasheet, 1.3V Main Supply Voltage can vary from 1.267V to 1.33V (which is -33mV / +30mV , -2.5% / +2.3%)
Customer must adhere to the 2.5% tolerance as much as possible. 1.3V needs to be as clean as possible and ripple free. This means that if customer is using switchers for 1.3V then he should know what he is doing. The VDD interface and the VDD GPO are not as crucial.
I'm using a switch mode power supply (SMPS) but the SMPS max output capacitance is small. Should I use LDOs or can I use less capacitance?¶
The following information is mostly for ADI applications use and we don't endorse it officially but it can help customers out of this sort of quandry. The ideal situation would be a DC/DC converter that could handle a lot of capacitance at it's output but this is rarely the case according to the SMPS data sheets. However, "2nd State Filter Design.pdf" file at the bottom of this page can help. It discusses how to incorporate a 2-stage filter inside the feedback loop of an SMPS. The final capacitor can be quite large (mF if necessary).
How can I reduce the spurs generated by my DC/DC converter? They seem to be getting into the RF portion of the system.¶
As mentioned above, we don't officially endorse a particular approach but something the customer may wish to examine is adding snubbers on the supply. The "Snubber Design.pdf" document at the end of this page shows how to do this.
Which ball supplies current to the reference oscillator input circuitry?¶
Reference oscillator input circuitry runs off of VDDA1P3_BB power domain (ball K4).