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DMA Speed

Question asked by wmaguire on Jul 21, 2013
Latest reply on Jul 22, 2013 by rejeesh

Hi all,

 

Looking at the DMA core specs for the Zynq device it looks like its max speed is 200MHz.   However, the samples from the ADC are at 245.76MSPS,

 

Assuming each 14 bit I/Q pair are scaled to 16 to produce a 32 bit I/Q word the through but on a 32 bit stream would be too high.  Therefore 64 bits are required where 2 consecutive samples are packed into the 64 bit word.  In this case the clock frequency would be 122.88MHz which is within the speed requirement for the DMA core.

 

If you look at the code in the module cf_adc_wr.v the I/Q are not packed as suggested above.  It looks like only 32 bits of the 64 bits are used. Therefore how is there sufficient BW in the DMA core to transfer the samples if only 32 bits of the available 64 bits are used?

 

 

always @(posedge adc_clk) begin

    adc_usr_sel_m1 <= up_usr_sel;

    adc_usr_sel <= adc_usr_sel_m1;

    adc_ch_sel_m1 <= up_ch_sel;

    adc_ch_sel <= adc_ch_sel_m1;

    adc_cnt <= adc_cnt + 1'b1;

    case (adc_ch_sel)

      2'b11: begin // both I and Q

        adc_valid <= adc_cnt[0];

        adc_data <= {adc_data_a_s, adc_data_b_s, adc_data[63:32]};

      end

      2'b10: begin // Q only

        adc_valid <= adc_cnt[1] & adc_cnt[0];

        adc_data <= {adc_data_b_s, adc_data[63:16]};

      end

      2'b01: begin // I only

        adc_valid <= adc_cnt[1] & adc_cnt[0];

        adc_data <= {adc_data_a_s, adc_data[63:16]};

      end

      default: begin  // user data

        adc_valid <= usr_data_valid;

        adc_data <= usr_data;

      end

    endcase

  end

 

 

Regards

 

 

Walter

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