Does ASRC support I2S input and TDM8 output?
The SRC has a 3-wire interface for the serial input and output ports that supports left-justified, I2S, and right-justified (16-, 18-, 20-, 24-bit) modes. Additionally, the serial interfaces support TDM mode for daisy-chaining multiple SRCs to form a frame .
Please refer to the ASRC chapter in the ADSP-214xx Hardware reference Manual for more details.
I wanted to ask almost the same question, but a bit more specific:
Can I use 4 ASRCs to have 4 x I2S inputs and get a TDM8 output signal at the same time?
That means, each ASRC is connected to an I2S input source and the output of the cascaded ASRCs is connected to a SPORT in TDM8 mode.
Is that possible?
I don't see anything mentioning this scenario in the manual.
Sorry for the delay in the response.
The above may not be possible . 4 ASRCs cannot have 4 x I2S inputs and get a TDM8 output signal at the same time.
My project has SPDIF input, the output SPORT is TDM8 format, clock slave to external.
Can I use ASRC in this scenario?
Can I use PCG to generate I2S clock from TDM8 external clock, then feed to ASRC output clock?
Can you kindly elaborate on what you are trying to do as I am not able to understand your requirements
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