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AD9852ASVZ - No internal update clock generated

Question asked by Simpson on Jul 18, 2013
Latest reply on Jul 25, 2013 by DSB

I'm new to using AD9852 and have difficulty starting it up. In conclusion, there seems to be no internal update clock generated upon POR. According to the datasheet, the update clock mode is internal upon POR. Therefore, if the reference clock is normally fed into the device, the internal update clock is supposed to start operating. I have attached the schematic, a test result and a snapshot of the differential reference clock inputs. Please look them over and give me any helpful comment. A summary of the attached is given as below.

 

1. Schematic

-. I made a mistake involving reference clock signal interface (LVDS to PECL without any translation)

-. So I added MC100LVEL16 to the relevant circuit as shown in the schematic of the evaluation board.

-. Now the differential reference clock inputs look okay. (Refer to the attached snapshot where the pair of reference clocks and their differential signal are plotted by means of the "Math" function of the scope.)

2. Test result

-. Configuration fails. The registers written seem to never apply to the system because no update clock bounces.

-. In addition, the path between the SPI driver(FPGA) and AD9852 is currently disconnected so as to avoid port direction conflict and prevent the UPDCLK port from being affected.

3. Differential reference clock inputs

-. As I stated in '1' above, I have installed MC100LVEL16 with some manipulation for level shift and modified the original circuit as shown in the schematic of the evaluation board in the datasheet.

-. The resultant differential signal seems to look fine. Nevertheless, no update clock comes out of Port 20(UPDCLK).

 

I would appreciate if anybody gives me some clues. Thank you for reading through!

 

best regards,

Shim

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