We're intend to use the AD9914 for the generation of frequency stepped signals. At this time we're implementing test scenarios using an FPGA and AD9914 Evalboard. The DDS is controlled via the parallel port in direct mode for (only) frequency modulation.
The scenario looks like this:
FPGA sets frequency (32bit) via parallel port and enables the frequency via io_update assertion. After a given number of SYNCCLK clocks the frequency is changed and again asserted by an IO/Update.
The SYNCCLK frequency is approximately 120MHz. The io_update is synchronously set up to the falling edge of SYNCCLK and lasts for ~5ns.
The frequency jumps works - almost - perfectly fine. The problem is the following: after triggering a new frequency, the new frequency appears at the output, then jumps to zero for a short while and then the signal appears again in a perfectly fine condition.
I've attached an oscilloscope screenshot that shows our problem.
We've set the "Autoclear Phase Accumulator" to one to have defined phase at the beginning of each frequency (we need the frequencies to be generated coherently!)
Can anyone suggest a possible solution for this problem?
Best Regards, Mikaelis.