I have heard that both xilinx and altera have code available to hook to ADI link ports, but a search of their sites only shows this for tigersharc. Does code exist for 21469?
Xilinx is preferred although I'd like to see both.
You are right Altera and Xlinx have FPGA code for link ports only for TigerSharc. These are not available for ADSP-21469.
Does ADI have anything to help a user bridge this gap to an FPGA? Is the 21469 similar enough to the tigersharc that this code would be found useful? Is there anything internal ADI has done that could be exploited?
The ADSP-21469 is actually more similar (but faster) to the 21161 link ports.
We have a plan to build a Altera Cyclone - ADSP-21469 DSP Module in our roadmap. We have lots of SHARC expertise. We have a ADSP-21369 + fpga design and several ADSP-21469 modules available now.
Here is a link to our dspblok products.
In addition to Danville Signal's off-the-shelf solutions, we also provide both custom solutions. We would be happy to discuss your application.
I have a same issue do you have some Benchank mark like AMI through put for Link port .
How many cycle does it take for a 32 bit word transfer .
The link port can transfer 8-bits(1 byte) in one LCLK. To transfer a 32-bit word it will need 4 LCLK cycles. The link port can operate up to 166 MHz max.
Hi jayathi ,
Do you have any bechmark data for Link port SHARC to SHARC data transfer .
Since this question has been answered through the private support, i think we can close this here in the forum.
Hi Tim ,
Did you get any information with regards FPGA code for 21369 .
Retrieving data ...