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AD9914 Synchronisation with extern divices

Question asked by BTS on Jul 12, 2013
Latest reply on Jul 31, 2013 by BTS

Hi.

I'm trying to synchronize the AD9914 eval board to an external device. Ii figured out, that the AD9914 doess not have a section about synchronization in it's manual. But as I read in other posts the AD9915 works the same way, and its manual describes a way of synchronizing multiple chips.

Please correct me if my asumptions are wrong.

The first asumption would be, that, in principle, there is no difference between a multiple chip synch and a synch to an external masterdevice. right?

 

Therefor i just need an external Masterdevice to synch the AD9914 to this device. right?

 

Since the synch-out of the AD9914 normally runs at 1/384 of the sysclock, a low frequency synch signal of 10MHz should work here.

 

Now to my questions.

First: I've read that the multichip synch just works for sys_clk of 2.5GHz or less. why is that the case? is it an sync_out problem, or a general problem with the ad9914?  Would it work to sync the ad9914 with a sys_clk of 3.5GHz to an external device? So that there is no need of an synch_out generation. Or is the Problem somewhere else, and a syncronization of systems above 2.5GHz can't be achieved?

 

second: In the description of the AD9915 is written so set some rigisterentries to activate the synch in channel. (Page 34 says to set the 0x1B[6] to logic high (Cal with SYNCH))

Since i asume the AD9914 is nearly the same i looked up at the manual, but there it says, unlike the AD9915, the the register 0x1B requires default settings. Do these settings have the same function as in the AD9915, namly sync in delay, syncout delay, and cal with sync? If yes i asume, that i can set them the way described in the AD9915 manual, so that the sync in is activated, and i can sync the ad9914 to another masterdevice.

right sofar?

 

The next question is the following. Does this syncronization just affect the output of the dds, or also the ... i call it data reading issues.

means the timing when the data is read of the parallel port for example (i would think yes, since we sync the sync_clk of the ad9914 to the external signal, and the sync_clk should be the timer for the reading of new data.)

As i Mentioned in another (yet unaswered post) before, i hope with will solve some data transfer problems i have.

 

and the last question would deal with multiple dds chips. If the sync with an external master device works, this also sould work for multiple ad9914 cards right? when i set the same sync signal to all ad9914 sync in, they sould all be synced to this master device right?

 

Thanks and with best regards

Daniel

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