I hope anyone of you can help me on this point.
I'm using a cyclic interrupt with the ADSP21469 and I monitor the isr period and duration with a processor output flag.
The interrupt period is 20us and it can be generated by the dsp timer or by a fpga connected to irq1.
Both case the behaviour is the same and I see a jitter of about 1.1us on isr start.
In particular, I see some isr calls are delayed of this quantity, while the next one is correct (namely, the average period is correct, 20us)
The anomaly gets worse if I execute the normal code in my application, while it almost disappears if I place a while(1) idle loop in the main function.
The behaviour is the same with normal interrupt or with fast interrupt (use of secondary registers, register isr with interruptf() functions)
I have the same code running on a ADSP21161 and I don't have this problem.