Thank you for everytime answer.
AD9122 is so difficult.
I have one question.
My system is below.
AD9122 internal pll is locked in user designed board.
I transmit 16bit sine wave data to DAC.
Fdacclk(DCI) is 100MHz. word interface mode.
Frefclk is 150MHz, N0 = 1, N1 = 8, N2 = 16.
So Fdacclk is 1.2G, Fvco is 1.2G.
But always occur FIFO warning, and DAC output signal is corruption.
I think cause is different FIFO read point and write point.
I think FIFO write point increased by Fdacclk.
And read point increased by Fdata(DCI).
If so, Fdacclk and Fdata same Frequency?