Hi, Just checking what might be a good upper frequency from a frequency source for the REF CLK when using the internal PLL?
If the PLL is enabled, the max REF CLK input frequency is 500MHz. That said, the REF CLK input divider must be set to 4 or 8 to satisfy not going over the max PFD rate of 125MHz. The minimum N register value is 10 for the PLL feedback register diviider. So, that works out to a minimum frequency multiplication of 20x. You should be OK running the PFD rate down to 5MHz, but I would not go any lower for stability reasons.
The PLL output (when enabled becomes the system clock, fs) is limited to a frequency range between 2.4GHz to 2.5GHz. Note, the total frequency multiplication of the internal PLL = 2N where N is the PLL feedback diviider value (8bits) in serial register 0x02. The times 2 in the formula represents a fixed /2 divider in the PLL feedback path, not shown in the present data sheet. The data sheet is being revised to reflect this overisght.This fixed /2 divider forces the total PLL frequency multiplication value to be an even number value, no odd available.
Given that PLL=2N, where N is 8bits, we have 2(255)=510.
2500MHz/510 = 4.9MHz. Can the AD9915 lock on to a minimum external frequency source of around 5MHz?
Next, let us say that N=1 2(1)=2
2500Mhz/2=1250Mhz Can the AD9915 lock on to a maximum externally applied frequency of 1250MHz?
or when the data sheet says "Maximum PFD rate of 125MHz", does that limit the choice of highest external frequency source to 125MHz or lower?
Thank you for your assistance
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