I'm trying to simulate the low frequency noise behaviour of the AD8000 CFA for a DC coupled application.
The question is: is the noise well modelled? I'm obtaining weird results while replicating the measurement conditions of the datasheet's figure 40 (input voltage noise plot). I expect a curve with a ~1/f slope from 10Hz up to about 100KHz with about 20nV/sqrtHz@10Hz down to a baseline of ~1.6nV/sqrtHz@100KHz, but the simulation shows a flat line around 1nV/sqrtHz up to 2MHz, and then the noise grows dramatically up to 20nV/sqrtHz@100MHz.
The simulation gives the same result using a 50Ohm source impedance.
Any suggestion on how to simulate the DC to 100KHz noise in this amplifier?
I attach the circuit and the input referred voltage noise plot.