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Question about the ADF4351 device.

Question asked by PaulKirby on Jul 7, 2013
Latest reply on Jul 16, 2013 by PaulKirby


I am trying to design a Triple (AM, FM) / Quadruple (SSB, CW) conversion superheterodyne Radio Transceiver for an Amateur radio project.


I was hoping to use two of these devices, one for my 1st Local Oscillator which generates 69.0415 MHz to 539.0115 MHz and the other for my 2nd Local Oscillator which generates 60 MHz.

I will be mixing a modulated 9.0115 MHz (FM) IF to the 60 MHz to produce my 2nd IF of 69.0115 MHz which is mixed with my 1st LO to produce 30 kHz to 470 MHz basically HF to UHF.


So I saw this device and I thought it would be nice to have it go as high as it can like the 35cm band etc, so I entered a start and end frequencies as 40 MHz and 1.0 GHz (giving me some leg room either side) which gave me an option of either 16 kHz or 4 kHz Phase detector, so I chose the inside 4 kHz which resulted in the following in ADIsimPLL:


Advanced Design - VCO Divider is Inside loop and set as follows:

Start Freq  Stop Freq   VCO Divider  Channel Spacing

40.0MHz    68.75MHz    64           1.00 Hz

68.75MHz    137.5MHz    32           1.00 Hz

137.5MHz      275MHz    16           1.00 Hz

  275MHz      550MHz     8           1.00 Hz

  550MHz     1.00GHz     4           1.00 Hz


So I thought great, just what I wanted.


Now in the Chip Programming Assistant when I entering the max frequency that ADIsimPLL said would work the tool told me that the INT was 250,000 and that FRAC was 0, I thought great, then I read in the datasheet for this device that the INT register was a 16 bit value i.e. 2^16 = 0 to 65,535 values.


So in a way I can't have it covering 40 MHz up to 1.0 GHz or higher using 1 Hz stepping or am I missing something ?


As far as I can see the max coverage that I should be able to to get to cover using a 4 MHz Reference with 1 Hz stepping is 40 MHz (my lowest required frequency) up to 262.143999 MHz (just under 50% of what I wanted for my highest required frequency)


I thought I could just set the INT, FRACT, MOD etc and then set the VCO divider to the required 5 values.


I understand why it prob won't work as I wanted due to (PFD * (INT + (FRAC/MOD)) = (4000 * (65535 + (3999 / 4000)) = 262.143999 MHz Max.


Or am I way off here, any help would be great.


Thanks in advance