I have some doubts about Clock Generation Unit(CGU), the followings are the doubts:
1,In Clock Generation Unit(CGU) section of the hardware reference document, the CGU PLL block diagram shows me the CCLK0 ,CCLK1 SCLK0, SCLK1 and DCLK. is CCLK1 can be assigned in core 0?
2,The DDR2 i used is split into two, one for core 0 and another for core 1. I have initial DDR2 in core 0, is it necessary to initial once again for the another part of DDR2?