We have an unusual architecture on a legacy board in that our 21161 is wired for a PROM boot. At present we have to have a running SHARC on the board to program the FLASH used for a PROM, so any issues in programming the PROM or any erroneous code bricks the board and requires using an ICE to re-program the FLASH to a known good state. This is problematic in many situations, i.e., the field, so we are exploring alternatives to improve the situation.
We have a second processor on the board that communicates with the 21161 via SPI which could easily hold an application image to download to the 21161 after it boots a kernel from the FLASH. This way the application updates would be done via the second processor which is more or less bullet-proof due to a locked boot-loader section, etc. This would offer us the ability to update the DSP application without significant concern about bricking boards in the field, etc.
Unfortunately none of the various manuals, example programs, boot loader kernels, etc. gives much of a clue as to what we would need to do to implement something like this. So my question is - has anybody else done something like this? Are we really out-in-the-woods trying to do a "cross-domain" boot like this? I can imagine grabbing pieces of the PROM boot kernel and combining them with other pieces of the SPI boot kernel, but even then it is not clear how the balance of the application gets loaded. If someone has already figured this out, or there is an application note to this end (I found nothing), I would greatly appreciate any help anyone can provide.