Per the datasheet, EE-349, and , the '21469 ODT output is static and once set stays on. This behavior is not compliant with the JEDEC DDR2 standard. Instead it seems that both the memory's and the SHARC's termination resistors will be connected to the byte lane signals at the same time. The bus will be double terminated and use lots of power. As such, the ODT is not usable. What am I missing?
- To other SHARC users: How have you used the ODT? Did it help?
- To ADI: please explain how the SHARC's ODT scheme was intended to be used.