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SHARC Clock In Freq and Core Rate vs. Incoming Clock Domains

Question asked by db10 on Jun 27, 2013
Latest reply on Jun 28, 2013 by Harshit.Gaharwar

I'm coming at this question from the perspective of how a Sigma DSP operates. In the Sigma DSP family, any incoming audio data into a serial port that is not synchronous to the Clock In pin of the Sigma DSP must be run through a sample rate converter before being processed in the Sigma DSP core. Clock input frequencies to the Sigma PLL are multiples of the LRCLK rate, e.g. 24.576 Mhz, 12.288 MHz.


A SHARC clock input would typically be driven at 25MHz so that with the PLL clock multiplier and register settings, the SHARC core could be run at the maximum rates of 400MHz or 450MHz. My question is: since a core running at a multiple of 25MHz is asynchronous to an incoming audio signal e.g. a 24.576MHz clock domain, do the audio signals into the SHARC core need to be sample rate converted first (as in the Sigma Processor)?