I made a PLL module using ADF4002 for 48MHz Clock but it has a problem. it's DLD output is moved to low level during frequency locking at high temp over 50deg. room temp and minus temp both DLD are operated well.
when I touched C2 of the loop filter at below figure, DLD is moved low to high. so I think that C2 of the loop filter is a causing with DLD.
firstly) I quested phase margin but phase margin of below simulation is 63deg and it does not happen spurious.
secondly) I doubt loop filter capacitors due to a little spurious than normal operated module.
in particularly, C2 of the loop filter is very sensitive at high temp over 50deg. if the cap is related with charge pump current, what kind of capacitor is the correct part?