Is a clock of 212.500 MHz brought by an LVDS connexion (CLK and _CLK_) enough to drive the two clock pins of the AD9958?
If not, how to bring to level?
A LVPECL signal is not to be considered, as I do not have the necessary -2V supply available.
I plan to use an ABRACON MEMS generator of that frequency, ASVMPLP-212.500MHz-LR
Thanks for the advice!