I'm implementing a SPI interface between the Blackfin BF534 and an FPGA. Blackfin is Master.
I want to read in 32 bytes from the FPGA using DMA.
I observe that after 32 bytes have been transfered and I get an interrupt, the Blackfin writes out additional SPI clocks - as long until I stop the SPI.
Problem is that the FPGA interprets the additional clocks as "more bytes requested" and shifts out additional data that is ignored by the Blackfin but should be sent on the next 32 bytes transfer.
My tests did not succeed in deactivating the SPI inside the Interrupt Service Routine fast enough to prevent the Blackfin's SPI to generate additional clock pulses.
How can I guarantee that the Blackfin only generates clock pulses for 32 bytes on each transfer?