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ADV7188 Default Config

Question asked by ChrisM Employee on Jun 25, 2013
Latest reply on Jul 5, 2013 by tamirci

1. I m using Panasonic WV-BP140 CCD camera whose paramaters are below


                510 (H) x 492 (V), 2:1 Interlace, 525 lines , 60 fields, 30 frame, H-> 15.75 kHz, V -> 60Hz


                Horizental resolution : 380 lines, EIA composite PAL output


 

 

    I feed the output of this camera into AIN1 as CBVS input.



2. From the ADV7188 datasheet  I assume it starts with following configuration


      Input Control : CVBS in AIN1 Autodetect PAL, NTSC, SECAM


      Video Selection : Enable Vsync, Enable Hsync


      Output Control : 8/10 bit interleaved output, 8 bit format LLC1 4:2:2 ITU R BT 656, output pins enabled


      Extended Output Control : HS, VS, FIELD three state, BT656-3


      ADI Control 2 : LLC pin active, Use 27 MHz crystal.


 

 

3. XTAL_TTL_SEL crystal is used to generate ADV7188 clock

 

 

 

4. EN28XTAL crystal frequency is 27 MHz

 

 

 

I m using TTL level oscillator instead of crystal and 28.63636 MHz freqency. So I need to set XTAL_TTL_SEL and EN28XTAL. But I'm a little confused on this. After the power up, the chip tries to use 27 MHz crystal altough not available. So there will be no clock referance. Therefore; I wonder how I will set XTAL_TTL_SEL and EN28XTAL when there is no clock supply. Do you think it can be performed by TWI SCLK ?

 

 

Second; I connected /OE to low and /RES pin to whole system Reset. For Analog Devices suggested power-up sequence I need to perform reset operation to the chip. But I wonder when I perform TWI reset does the chip drive /RES pin to low ? If so, whole system will be reset which will cause everything start again. Do you think /RES pin is input and TWI reset can not drive /RES pin to low?

 

 

 

I'm trying to implement following scenario

 

 

 

CVBS - > ADV7188_AIN1 -> BT656 (LLC1_4:2:2_Y,Cb,Cr)  (I think cysnc, hsync, field is also active)-> BF537_PPI

 

 

Thank you for your time.

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