I am considering to use AD9129 for my application.
There are a few things that I want to know
1) maximum data sampling rate (not dac update rate)
Our data signal bandwidth is up to 2GHz. So we need to have at least 4GSPS data sampling DAC.
According to the AD9129 datasheet, it says that maximum data rate is up to 2.8GSPS
But is also says it supports up to 5.6GSPS, which is dac update rate.
which one is correct to cover the signal of 2GHz bandwidth?
2) FPGA to AD9129 interface connection
If AD9129 can supports 4GSPS data sampling rate,
data interface clock (from FPGA) to DAC is 1GHz when digital input data is DDR operation ?
DAC main clock (DACCLK_x port in AD9129) is 2GHz ?
Is there any way to use 500Mhz data interface clock to have 4GSPS data sampling rate in AD9129.