I use ADIsimCLK for the first time, and I have some questions about the usage.
(1) How should I determine the best loop filter for a given application?
ADIsimCLK provide a default value of the loop bandwidth to get the simulation going and suggest to change this value later. How should I know the best loop bandwidth and phase margin for my application?
(2) How could I add specific phase noise to the reference clock?
The software provide 4 kind of phase noise to the simulation, and they are None, Center/Floor, Point/Floor and Lesson. Sorry, I can not find the exact meaning for the later three words. Besides, if I want to evaluate the influence of the phase noise of reference clock to the output clock, what should do? For example, if I have a reference clock with a integrated RMS jitter 500fs, how can I add the phase noise to the simulation environment?
(3) For some other jitter cleaner application, they often design the loop bandwidth to tens of Hz. Why for AD9525, we design the loop filter bandwidth to kilos of Hz?