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ADF4106 Simulation Register Settings vs Reality

Question asked by ChrisH Employee on Apr 29, 2010
Latest reply on Sep 10, 2010 by dawid.powazynski

Using both  ADIsimPLL and the on-line interactive design tool (  http://designtools.analog.com/dt/rfpll/adf411X.html ) trying to produce a VCO Freq of 5.767 GHz, 25kHz channel spacing, 20MHz clock (on the interactive tool, screenshot attached).

After changing the ininilization latch prescaller from 8/ to 32/33 (as shown), and uploading the register settings to my board, I get 5.934GHz instead.

 

I get similar (though slightly different) results if I do it in SimPLL.

 

Ideas?

 

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