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ADAU144x Possible wrong pin numbering in documentation?

Question asked by Svilen on Apr 29, 2010

While designing the IC component for the DSP in my CAD software, I found some info in documentation that confuse me.

According to last documentation ADAU1442_1445_1446 revision B, on table 27 "Output Clock Domain Assignments in Master Mode" is written that data out pins 0,1,2 are linked to clocks 9,10,11.

At other side, looking in pin configuration at figure 7, where all data and clock pins are close each other, data out pins 0,1,2 are near to clock pins 3,4,5 and data out pins 6,7,8 are near to clock pins 9,10,11.


Is it any mistake in documentation, or there is exception of "close data and clock pins" on pins configuration.