The AD9102 seems able to store command register values even without a DAC clock supplied. In fact the PAT_STATUS register will change from 0x0001 to 0x0003 if the /TRIGGER pin is provided a falling edge. Is this correct operation?
You will be able to program the DAC because of the CLK of the SPI communication (SCLK).
The RUN bit in the PAT_STATUS register is responsible for pattern generation. You can still set this even without the DAC CLK. However, if the register value 0x1E changes from 0x0001 to 0x0003, that means the pattern generator is in the on state (PATTERN bit = 1). That should not be happening since there is a set-up time needed between DAC CLK rising edge and \TRIGGER falling edge. Kindly check if there is a glitch somewhere in the CLKP input that causes it.
Thanks Sitti. Good to know that the registers are programmable using SPI without a DAC CLK signal.
The PAT_STATUS register (0x1E) will change from 0x0001 to 0x0003 (PATTERN bit=1) even if the clock is disabled. In this case the CLKP/N signals are both sitting at ~0.9V and quiet as expected. Could it be that the register is directly updated from the /Trigger transition but that the internal circuits require the DAC CLK to read the register?
As of the moment, I only have the datasheet to refer to.
Have you accessed the pattern_delay register (0x20) prior to trigger low?
If not, after reset, the default value of PATTERN_DELAY is 0x000E.
The diagram shows that the register will only set the PATTERN bit to 1, after the (tsu) set-up time between trigger falling edge and CLKP/N rising edge and tdly is satisfied. However, I did not find any value for this tsu.
I would have to check with my colleague regarding this.
I'll get back to you as soon as possible.
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