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AD9129-EBZ, ML-605 Reference design, Loading user samples to SDRAM

Question asked by aerskine on Jun 21, 2013
Latest reply on Jun 21, 2013 by rejeesh

Hello

 

My customer has the AD9129-EBZ board connected to the ML-605 via the DAC FMC Interposer board.

 

He is using the ADI Reference Design for the ML-605, which is available on http://wiki.analog.com/resources/fpga/xilinx/interposer/ad9129

 

On the Wiki page there is the following description:

“Functional descriptionThe reference design consists of a DDS module and a lvds interface.
The DDS module consists of a Xilinx IP core and a DDR-DDS. Internally the DDS runs at fDAC/3 clock. The DDR-DDS allows any pattern to be generated in the memory to be driven to the DAC. The output samples are interleaved and driven by the lvds interface.”

 

The aim is to use store the desired array of samples into DDR3 Memory (interleaved samples) and use the DDR-DDS to clock the data from DDR3 into the DAC, as described in the functional description above.

 

From the documentation on the Wiki Site, and the source code , it is not clear how to modify the project to

a) store a set of sample data into the DDR3 e.g. in an initialisation phase of the program
and

b) set up the DDS block to point to the appropriate location in DDR3, where the data was written.

 

Q1. What changes need to be made to the project, to get the basic DDR-DDS functionality to work, as opposed to the Xilinx DDS core?

 

Q2. How is it possible to include a file of users 14-bit DAC sample data in the project and instruct the compiler to place it in DDR3?
How should the data be formatted?

How many samples can be stored in SDRAM in this way?
What changes need to be made to the project, to point the DDR-DDS function to the location and length of the user's Sample data

 

Thanks and best regards

aerskine

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