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Can not clear SPORT RX FIFO

Question asked by lekigo on Jun 21, 2013

Hello.

I am receiving data from SPORT0 and SPORT1 in BF534 processor by use of DMA. And I simulate receiving noise data by one of devices by following method. SPORT0 is a master, that is it's generating CLK and frame signals. I have configured DMA's for one shot (FLOW = STOP). DMA for SPORT0 generates an interrupt after completing. DMA block for SPORT1 is less by 2 - 8 words than for SPORT0. After DMA for SPORT1 completes, it stops, but SPORT0 continues to generate signals. So SPORT1 continues to receive and its FIFO is filling. After DMA for SPORT0 completes it rase an interrupt. In the interrupt I disable SPORT0 so no more data are receiving by SPORTs. Then, I try to clear SPORT1 FIFO by reading its content by 16bit words 16 times and more. But RXNE status bit still shows that there is a data in the FIFO. Same behavior I detect when similar experimenting with SPI.

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