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Difficulties with AD9102 producing output signal

Question asked by johnvanloon on Jun 20, 2013
Latest reply on Jul 30, 2017 by ahmad14101370

My initial concerns dealt with the DAC clock. Several different configurations have been attempted.

 

I am not seeing an output from the Iout after setup. It is a custom board but very simple application of the AD9102 chip itself.

 

Included is the schematic. Note it is missing the control header for the /trigger signal. The clock input has been modified to a standard oscillator and the clock signals are provided as seen on the AD9102 clock P/N pins.

 

During testing I noticed that removal of the clock signal does not affect ability to write registers via SPI. Is this correct?

 

Set up for sine wave output.

Register settings are as follows (read back from chip after a write): (/Trigger is high)

         SPI CONFIG : 0x0000          POWER CONFIG : 0x0607

         CLOCK CONFIG : 0x0700                REF ADJ : 0x0000

            DAC AGAIN : 0x0020              DAC RANGE : 0x0000

             DAC RSET : 0x1f0a             CAL CONFIG : 0x0000

          COMP OFFEST : 0x4000             RAM UPDATE : 0x0000

           PAT STATUS : 0x0001               PAT TYPE : 0x0000

        PATTERN DELAY : 0x000e                DAC DOF : 0x0000

          WAVE CONFIG : 0x0031           PAT TIMEBASE : 0x0111

           PAT PERIOD : 0x8000                DAC PAT : 0x0101

           DOUT START : 0x0003            DOUT CONFIG : 0x0000

              DAC CST : 0x0000               DAC GAIN : 0x0000

           SAW CONFIG : 0x0404               DDS TW32 : 0x002b

              DDS TW1 : 0xb100                 DDS PW : 0x0000

               TW SEL : 0x0002             DDS CONFIG : 0x0000

        TW RAM CONFIG : 0x0000            START DELAY : 0x0000

           START ADDR : 0x0000              STOP ADDR : 0x0000

              DDS CYC : 0x0001              CFG ERROR : 0x0000

 

After Trigger Pulled low:

          SPI CONFIG : 0x0000          POWER CONFIG : 0x0e07

         CLOCK CONFIG : 0x0700                REF ADJ : 0x0000

            DAC AGAIN : 0x0020              DAC RANGE : 0x0000

             DAC RSET : 0x1f0a             CAL CONFIG : 0x0000

          COMP OFFEST : 0x4000             RAM UPDATE : 0x0000

           PAT STATUS : 0x0003               PAT TYPE : 0x0000

        PATTERN DELAY : 0x000e                DAC DOF : 0x0000

          WAVE CONFIG : 0x0031           PAT TIMEBASE : 0x0111

           PAT PERIOD : 0x8000                DAC PAT : 0x0101

           DOUT START : 0x0003            DOUT CONFIG : 0x0000

              DAC CST : 0x0000               DAC GAIN : 0x0000

           SAW CONFIG : 0x0404               DDS TW32 : 0x002b

              DDS TW1 : 0xb100                 DDS PW : 0x0000

               TW SEL : 0x0002             DDS CONFIG : 0x0000

        TW RAM CONFIG : 0x0000            START DELAY : 0x0000

           START ADDR : 0x0000              STOP ADDR : 0x0000

              DDS CYC : 0x0001              CFG ERROR : 0x0000

 

Screen shot of ~OUT yellow and clockP blue from scope. ClockN is biased with 39k ohm in parallel with 0.1 uF. The clock is generated from a std 40 MHz crystal oscillator not the 150 MHz LVDS clock shown in the schematic.

 

ClockP blue and N yellow signals.

 

 

The program executes the SPI writes:

     // Need TW value to set frequency.

         // Fo=DDS_TW*Fclk/2^24

         // Input clock 150 MHz

         // Fo=100kHz

         // DDS_TW=(2^24)*10^5/(150*10^6)=11184.8

         // DDS_TW=11185=0x002BB1, Fo=100001.7 Hz

         // note the resolution is ~ 4.5 Hz

     // configure WAV_CONFIG register

         // WAVE_SEL 01 - prestored waveform

         // CH_ADD 0

         // PRESTORE_SEL 11 - DDS output

         // WAV_CONFIG = 0x0031

     // Set PATTERN_RPT to 0 in PAT_TYPE for continuous repeat (0x0000)

     // set Analog gain to 1 in DAC_GAIN field of DACAGAIN register (0x0020)

     // set trigger delay only for the first in TRIG_TW_SEL (0x0002)

     // Turn on the RUN bit in PAT_STATUS register (0x0001)

     // Finish by updating registers. UPDATE=1 in RAMUPDATE register (0x0001)

     uint8_t spi_data_tx[5];

     ioport_set_pin_level(AD9102_nTRIGGER,1);

     ioport_set_pin_level(AD9102_CLK_EN,1);

     ioport_set_pin_level(AD9102_nCS,0);

     ioport_set_pin_level(AD9102_nRESET,1);

 

     // Set TW value

     spi_select_device(&SPIE, spi_device_conf);

     spi_data_tx[0]= 0x00;

     spi_data_tx[1]=(char) AD9102_DDS_TW1;

     spi_data_tx[2]= 0xB1;

     spi_data_tx[3]= 0x00;

     spi_write_packet(&SPIE, spi_data_tx, 4);

     spi_deselect_device(&SPIE, spi_device_conf);

     spi_select_device(&SPIE, spi_device_conf);

     spi_data_tx[0]= 0x00;

     spi_data_tx[1]=(char) AD9102_DDS_TW32;

     spi_data_tx[2]= 0x00;

     spi_data_tx[3]= 0x2B;

     spi_write_packet(&SPIE, spi_data_tx, 4);

     spi_deselect_device(&SPIE, spi_device_conf);

    

     // Configure WAV_CONFIG register

     spi_select_device(&SPIE, spi_device_conf);

     spi_data_tx[0]= 0x00;

     spi_data_tx[1]=(char) AD9102_WAVE_CONFIG;

     spi_data_tx[2]= 0x00;

     spi_data_tx[3]= 0x31;

     spi_write_packet(&SPIE, spi_data_tx, 4);

     spi_deselect_device(&SPIE, spi_device_conf);

    

     // Set Pattern Repeat in PAT_TYPE

     spi_select_device(&SPIE, spi_device_conf);

     spi_data_tx[0]= 0x00;

     spi_data_tx[1]=(char) AD9102_PAT_TYPE;

     spi_data_tx[2]= 0x00;

     spi_data_tx[3]= 0x00;

     spi_write_packet(&SPIE, spi_data_tx, 4);

     spi_deselect_device(&SPIE, spi_device_conf);

 

     // Set Analog Gain

     spi_select_device(&SPIE, spi_device_conf);

     spi_data_tx[0]= 0x00;

     spi_data_tx[1]=(char) AD9102_DACAGAIN;

     spi_data_tx[2]= 0x00;

     spi_data_tx[3]= 0x20;

     spi_write_packet(&SPIE, spi_data_tx, 4);

     spi_deselect_device(&SPIE, spi_device_conf);

 

     // Set trigger delay only for first

     spi_select_device(&SPIE, spi_device_conf);

     spi_data_tx[0]= 0x00;

     spi_data_tx[1]=(char) AD9102_TW_SEL;

     spi_data_tx[2]= 0x00;

     spi_data_tx[3]= 0x02;

     spi_write_packet(&SPIE, spi_data_tx, 4);

     spi_deselect_device(&SPIE, spi_device_conf);

 

     // Turn on the run bit

     spi_select_device(&SPIE, spi_device_conf);

     spi_data_tx[0]= 0x00;

     spi_data_tx[1]=(char) AD9102_PAT_STATUS;

     spi_data_tx[2]= 0x00;

     spi_data_tx[3]= AD9102_RUN_BIT;

     spi_write_packet(&SPIE, spi_data_tx, 4);

     spi_deselect_device(&SPIE, spi_device_conf);

 

     // Update the registers

     spi_select_device(&SPIE, spi_device_conf);

     spi_data_tx[0]= 0x00;

     spi_data_tx[1]=(char) AD9102_RAMUPDATE;

     spi_data_tx[2]= 0x00;

     spi_data_tx[3]= 0x01;

     spi_write_packet(&SPIE, spi_data_tx, 4);

     spi_deselect_device(&SPIE, spi_device_conf);   

Outcomes